1. Field of the Invention
The present invention generally relates to a voltage-controlled oscillator circuit and a voltage-controlled oscillating method, capable of changing an oscillating frequency in response to an externally supplied control voltage. More specifically, the present invention is directed to a technique suitable for realizing a voltage-controlled oscillator circuit by employing a phase-locked loop (PLL) circuit.
2. Description of the Related Art
Conventionally, this sort of voltage-controlled oscillator circuit is known as, for instance, a circuit shown in FIG. 1. This conventional voltage-controlled oscillator circuit is described more in detailed, for example, in "3 GHz GaAs PLL clock pulse generator" written by T. OKUYAMA and T. ENOMOTO, Shingaku-Giho No. ED93-152 published by the institute of Electronics, Information and Communication Engineers in JAPAN.
As indicated in FIG. 1, the conventional voltage-controlled oscillator circuit has inverters 101.sub.1 to 101.sub.3. These inverters 101.sub.1 to 101.sub.3 invert a polarity of a signal entered from an input terminal T.sub.I, and output the polarity-inverted signal from an output terminal T.sub.O. In general, such a circuit is referred to as a "ring oscillator". This ring oscillator is constituted by connecting the odd number (three inverters in FIG. 1) of inverters in a ring shape.
That is, the first inverter 101.sub.1 is constituted by an enhancement-mode field-effect transistor (E-FET) QE1, a first depletion-mode field-effect transistor (D-FET) QD1, and a second depletion-mode field-effect transistor QD2. A source electrode S of the E-FET QE1 is connected to the ground potential, and a gate electrode G thereof is connected to the input terminal T.sub.I. A gate electrode G of the first D-FET QD1 is connected to a drain electrode of the E-FET QE1, and a source electrode S of this first D-FET QD1 is connected to this drain electrode of the E-FET QE1, and also a drain electrode D thereof is connected to a power supply Vd. A source electrode S of the second D-FET QD2 is connected to the drain electrode D of the E-FET QE1, and a drain electrode D of this second D-FET QD2 is connected to the power supply Vd. Both a drain electrode D of the E-FET QE1 and a source electrode S of the first D-FET QD1 are connected to the output terminal T.sub.O, and a gate electrode G of the second D-FET QD2 is connected to a voltage control terminal Tc. A control voltage Vc used to vary an oscillating frequency is applied to this voltage control terminal Tc. It should be noted that the structures of the inverters 101.sub.2 and 101.sub.3 are identical to the structure of the above-explained inverter 101.sub.1.
In this ring oscillator circuit arrangement, the E-FET QE1 among the respective structural elements of the inverter 101.sub.1 is operable as a driver circuit for driving the next-staged inverter 101.sub.2, and the first D-FET QD1 constitutes a load of this E-FET QE1. The load current flowing through the inverter 101.sub.1 may be controlled by connecting the second D-FET QD2 in parallel to this load transistor, namely the first D-FET QD1. In this inverter 101.sub.1, a current established by summing a constant current flowing through QD1 with a variable current (variable by control voltage V.sub.c) flowing through QD2 will flow. This summed current may determine the propagation delay time "tpd" of the inverter 101. Both the inverter 1012 and the inverter 101.sub.3 are operable in a similar manner to that of the above-explained inverter 101.sub.1.
Since the oscillating frequency of the voltage-controlled oscillator circuit is varied in response to the propagation delay time of the overall circuit arrangement, this oscillating frequency can be controlled based upon the control voltage V.sub.c. For instance, when the current flowing through the second D-FET QD2 is decreased by lowering this control voltage V.sub.c, the pull-up ability of QD2 with respect to the power supply Vd is weakened. As a result, the propagation delay time tpd of each of the inverters is increased, so that the oscillating frequency of the voltage-controlled oscillator circuit is lowered. Conversely, when the current flowing through the second D-FET QD2 is increased by increasing the control voltage V.sub.c, the pull-up ability thereof with respect to the power supply Vd is strengthened. As a result, the propagation delay time tpd of each of the inverters is decreased, so that the oscillating frequency of the voltage-controlled oscillator circuit is increased.
FIG. 2 is a diagram for showing a relationship of the oscillating frequency with respect to the threshold voltage Vt of the D-FET used in a voltage-controlled oscillator circuit similar to the voltage controlled oscillator circuit indicated in FIG. 1, namely a graphic representation for indicating a permitted variation range of the threshold voltage Vt by which the conventional oscillator circuit can be oscillated at various frequencies. An abscissa of the graphic representation shown in FIG. 2 indicates a threshold voltage [V] of the D-FET, whereas an ordinate thereof represents an oscillating frequency [GHz] (VCO oscillating frequency) of this voltage-controlled oscillator circuit. In other words, FIG. 2 represents a simulation result of a permitted variation range for various threshold voltages at which the conventional voltage-controlled oscillator can be oscillated in various frequencies, while varying the control voltage from 0.1V to 0.8V. In this simulation, as with this conventional voltage-controlled oscillator circuit, a ring oscillator arranged by 9 sets of inverters with employment of GaAs D-FETs and GaAs E-FETs is employed. Also, the power supply voltage is selected to be 2[V].
As indicated in FIG. 2, in the case that the conventional voltage-controlled oscillator circuit is oscillated at the frequency of 1[GHz], the permitted variable range of the threshold voltage Vt of the D-FET is defined from -0.70[V] to -0.30[V], namely 0.40[V].
There are some possibilities that the threshold voltage Vt of the D-FET is shifted, or deviated from the designed value, because of fluctuations occuring when this D-FET is manufactured. In this case, while the gate-to-source voltage V.sub.gs of the first D-FET QD1 which constitutes the inverter is a constant voltage (=0[V]), since the value of the current flowing through the first D-FET QD1 is varied, the oscillating frequency is shifted from a desirable frequency.
A voltage-controlled oscillator circuit is mainly employed in a loop of a PLL circuit, and is required to be oscillated at a preselected frequency (for example, 1[GHz]) in response to an input voltage. However, there is a certain possibility that when the above-explained voltage-controlled oscillator circuit is employed in a PLL circuit, since the permitted variation range of the threshold voltage Vt of the D-FET is narrow, this voltage-controlled oscillator cannot be oscillated under stable condition.
As the related art, for instance, Japanese Laid-open Patent Disclosure (JP-A-Heisei 6-334515) discloses "PHASE-SYNCHRONIZED OSCILLATOR CIRCUIT". In this phase-synchronized oscillator circuit, a ring oscillator is arranged by the first to fifth inverter chains, the basic inverter chain, and the first to fifth selectors. In the first to fifth inverter chains, 2 sets of inverters; 4 sets of inverters; 8 sets of inverters; 16 sets of inverters; and 32 sets of inverters are series-connected to each other respectively. In the basic inverter chain, the even numbers of inverters are series-connected to each other. The first to fifth selectors control whether or not each of these first to fifth inverter chains is engaged into the loop. Also, this phase-synchronized oscillator circuit is arranged by the phase comparing circuit, and the up/down counter. The phase comparing circuit compares the phase of the input clock signal with the phase of the oscillator clock signal produced from the ring oscillator. The up/down counter counts up/down the oscillator clock signal in response to the output signal derived from this phase comparing circuit. In response to the signal supplied from this up/down counter, the first to fifth selectors are controlled so as to synchronize the phase of the oscillator clock signal with the phase of the input clock signal.
Also, Japanese Laid-open Patent Disclosure (JP-A-Heisei 5-136657) discloses "RING OSCILLATOR CIRCUIT". In this ring oscillator circuit, the first ring oscillator is constituted in such a manner that the first to fifth inverters are series-connected to each other and connected in a ring shape while these inverters sandwich the N-channel transistor. Also, as the path for shortcutting the series connection of these first to fifth inverters, the P-channel transistor is provided between the cathode of the first inverter and the anode of the third inverter. The respective N-channel and P-channel transistors are ON/OFF-controlled in order to switch the stage number of the inverters.
Also, Japanese Laid-open Patent Disclosure (JP-A-Heisei 7-254847) discloses "OSCILLATOR CIRCUIT AND PLL CIRCUIT". In this oscillator circuit/PLL circuit, the ring oscillator is constituted as follows. That is, a plurality of inverters are connected in the multiple stages, the signals are derived from the odd-numbered inverters including the final-staged inverter, and these derived signals are fed back via the selector to the input terminal of the first-staged inverter. Also, current may be supplied via the current-controlling MOSFETs to the respective inverters. In this oscillator circuit/PLL circuit, the signals which should be fed back to the input terminal of the first-staged inverter are switched by the selector so as to largely vary the oscillating frequency. Also, the oscillating frequency is fine adjusted by changing the gate voltage of the current-controlling MOSFET.
Furthermore, Japanese Laid-open Patent Disclosure (JP-A-Showa 61-65620) discloses "OSCILLATOR CIRCUIT". This oscillator circuit is equipped with the first inverter series, the second inverter series, and also the inverter series switching means. In the first inverter series, the even-numbered inverters are series-connected to each other in a ring shape. In the second inverter series, a predetermined number of inverters are series-connected to each other. In response to the externally-supplied signal, the inverter series switching means may switch a portion of the first inverter series and the second inverter series.
Moreover, Japanese Laid-open Patent Disclosure (JP-A-Showa 60-62147) discloses "BIAS VOLTAGE GENERATING CIRCUIT". In response to the condition of the memory, such as the standby condition, this bias voltage generating circuit switches the stage number of the inverters for constituting the ring oscillator. Since the stage number of these inverters is varied, the unnecessary power consumption of the memory during the standing condition can be suppressed.
However, none of the above-described conventional techniques considers the permitted variable range of the threshold voltage for the depletion-mode field-effect transistor used in the inverter. Therefore, these conventional techniques could not solve the above-explained problem. That is, when this threshold voltage is largely shifted from the designed value, stable oscillation cannot be realized.